IEEE 41st International Symposium on Multiple-Valued Logic - ISMVL 2011

The Multiple-Valued Logic Technical Committee of the IEEE Computer Society will hold its 41st annual symposium on May 23-25, 2011, in Tuusula, Finland.

The symposium will be co-located with the 19th International Workshop on Post-Binary ULSI Systems and Reed-Muller 2011 Workshop.

You are invited to submit an original paper, survey or tutorial paper on any subject in the area of multiple-valued logic, including but not limited to:

  • Algebra and Formal Aspects
  • ATPG and SAT
  • Automatic Reasoning
  • Circuit/Device Implementation
  • Communication Systems
  • Computer Arithmetic
  • Data Mining
  • Fuzzy Systems and Soft Computing
  • Image Processing
  • Logic Design and SwitchingTheory
  • Logic Programming
  • Machine Learning and Robotics
  • Mathematical Fuzzy Logic
  • Nano Technology
  • Philosophical Aspects
  • Quantum Computing
  • Signal Processing
  • Spectral Techniques
  • Verification

A selection of the papers presented at the ISMVL 2011 will be invited to provide an extended version to be published in a special issue of the Journal of Multiple-Valued Logic and Soft Computing.

Final Paper Submission:

As in the previous years, the Proceedings of ISMVL 2011 will be published by the IEEE Press.

Detailed instructions on how to submit a FINAL version of the paper can be found at the following [link]

For Authors:

To see comments by reviewers pleas use the following [link]

For Reviewers:


Important dates:

Paper submission, December 1, 2010 (extended deadline)
Author notificationFebruary 10, 2011
Final versionMarch 1, 2011
Early registration deadlineApril 10, 2011
ISMVL 2011 SymposiumMay 23-25, 2011